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Table 1 Processor configuration and Clock frequency assumptions

From: An energy-delay product study on chip multi-processors for variable stage pipelining

Parameters Alpha 21264 processor
Fetch, issue, commit-width 4,4 (int), 2 (float), 11
Reorder buffer size 80
Issue window 20 (int), 15 (float)
Load/store queue 32 (load), 32 (store)
Register file 160
Floating-point ALU 1 adder, 1 multiplier
Integer ALU 4 adder, 4 multiplier
L1 Data, instruction-cache 512642
Dtlb, Itlb 164128, 132128 (fully associative)
Clock frequency rate f(\(\beta _1=1\), \(\beta _2=1.5\), \(\beta _3=2\)) 100 %, 66.7 %, 50 %