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Erratum to: An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUs

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The original article was published in Human-centric Computing and Information Sciences 2015 5:2

Erratum

In the original published version of this article [1], the third co-author’s name Kothari Dwarkadas Pralhaddas appears twice, and the name of the second co-author Alagan Anpalagan is missing. The correct author list is as follows:

Vijayalakshmi Saravanan, Alagan Anpalagan, Kothari Dwarkadas Pralhaddas and Isaac Woungang

The publisher apologies for this error introduced during publication of this article.

Reference

  1. 1.

    Saravanan V, Pralhaddas KD, Kothari DP, Woungang I (2015) An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUs. Human-Centric Comput Inf Sci 5:2

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Author information

Correspondence to Vijayalakshmi Saravanan.

Additional information

The online version of the original article can be found under doi:10.1186/s13673-014-0016-8.

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Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (https://creativecommons.org/licenses/by/4.0), which permits use, duplication, adaptation, distribution, and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

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Saravanan, V., Anpalagan, A., Pralhaddas, K.D. et al. Erratum to: An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUs. Hum. Cent. Comput. Inf. Sci. 5, 9 (2015) doi:10.1186/s13673-015-0026-1

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